1. Technical Field
Various embodiments generally relate to a data alignment device, and more particularly, to a technology capable of ensuring a margin of alignment data.
2. Related Art
With an increase in the degree of integration, semiconductor memory devices have been continuously improved in order to improve an operation speed thereof. There has emerged a so-called synchronous memory device capable of operating synchronously with a clock applied from an exterior of a memory chip in order to improve an operation speed thereof.
The first proposed device is a so-called SDR (single data rate) synchronous memory device that inputs and outputs one data through one data pin over one clock cycle from an exterior of the memory device synchronously with a rising edge of the clock. However, the SDR synchronous memory device is not sufficient for satisfying the speed of a system requiring a high speed operation.
Particularly, a data processing speed of a central processing unit (CPU) has gradually increased and a system for supporting multi-media has increased. In a semiconductor memory device, there have been continued attempts for increasing a bandwidth of a synchronous memory device with an increase in the degree of integration and improving an operation speed of the semiconductor memory device.
In this regard, there has been proposed a DDR (double data rate) synchronous memory device that processes two pieces of data in one clock cycle. Through each data input/output pin of the DDR synchronous memory device, two pieces of data are continuously inputted/outputted in synchronization with a rising edge and a falling edge of a clock inputted from an exterior.
Accordingly, since the DDR synchronous memory device may ensure a bandwidth of more than twice a minimum without increasing a frequency of a clock as compared with the conventional SDR synchronous memory device, a high speed operation may be performed.
A data strobe signal used in a data write operation of the DDR synchronous memory device is called a write data strobe signal (WDQS). The write data strobe signal (WDQS) substantially maintains a low level state in advance before a predetermined clock cycle (for example, one clock cycle (1tCK)) in which data is inputted. The write data strobe signal (WDQS), which is subject to clocking in response to a time at which data is inputted, substantially maintains a low level state during the predetermined clock cycle after all pieces of data are inputted, and transitions to a high level state.
The tCK is a unit indicating a clock cycle. Data, which is inputted by matching a set-up time and a hold time with one write data strobe signal (WDQS) inputted from an exterior, is stored in the DDR synchronous memory device.